Devices in integrated circuits are frequently subject to various types of degradation. For example, p-channel field effect transistors (pFETs) may be affected by Negative Bias Temperature Instability (NBTI) due to a negative gate bias applied to the pFETs for prolonged periods of time. The NBTI may cause the threshold voltage of the pFETs to rise due to the creation of lattice imperfections at the boundary of the oxide and silicon.
One type of circuit that may experience problems due to NBTI degradation and its associated effects is a clock distribution circuit in which the transitioning of the clock between logic high and low can be selectively disabled. A clock distribution circuit with many inverters connected in series, for example, may have its input selectively disabled in order to conserve power that would otherwise be consumed by continuously transitioning the series-connected inverters. The input to the clock distribution circuit may be selectively disabled by, for example, using a control gate (e.g., a NAND gate) and a control signal (e.g., an enable signal). Where a NAND gate is used as the control gate, the clock and enable signals are input to the NAND gate and the output of the NAND gate is provided as the input to the clock distribution circuit. The input to the clock distribution circuit may be disabled by bringing the enable signal to logic low in order to assure that, regardless of the clock signal, the input to the clock distribution circuit is always logic high. When the input to the clock distribution circuit is logic high, every other inverter will have a conductive pFET and a non-conductive nFET, with the alternating inverters having a non-conductive pFET and a conductive nFET. In this state, the pFET of every other inverter may experience NBTI degradation when the clock transitioning is disabled, while the pFETs of the alternating inverters may not similarly degrade. If the input to the clock distribution circuit is always disabled as logic high, the same pFETs will always experience NBTI degradation, while the other pFETs will not experience NBTI degradation during the disabled state of the clock distribution circuit. The uneven degradation of the pFETs may cause duty cycle distortions on clock signals that are subsequently propagated through the clock distribution circuit.
Furthermore, in addition to NBTI, several other types of degradation can affect various operating characteristics of pFETs and/or nFETs, such as their saturation current, threshold voltage, channel mobility, leakage, and so forth. Some of these degradation processes may, similar to NBTI, unevenly wear the pFETs and/or the nFETs depending on the disabled states of the pFETs and/or the nFETs. As just one example of another type of degradation, Carrier Hot Channel (CHC) may affect both nFET and pFET devices. As with NBTI, these other degradation processes may alter the operating characteristics of the pFETs and/or nFETs, which may ultimately distort the duty cycle of a subsequently propagated clock signal or otherwise cause problems.